(1) Field of the Invention
The present invention relates to the fabrication of dynamic random access memory (DRAM) devices, and more particularly to a method for fabricating stacked storage capacitors for DRAM cells using an improved semiconductor process. Openings in a disposable insulating layer are used as a template for making capacitor bottom electrodes. This process eliminates erosion of an underlying insulating layer over the devices on the substrate when these openings are misaligned.
(2) Description of the Prior Art
Ultra Large Scale Integration (ULSI) technologies have dramatically increased the circuit density on the semiconductor chip. This increase in density is due in part to advances in high-resolution photolithography and anisotropic plasma etching in which the directional ion etching results in essentially bias-free replication of the photoresist image in the underlying patterned layers, such as in polysilicon and insulating oxide layers and the like.
One such circuit type where this high-resolution processing is of particular importance is the dynamic random access memory (DRAM) circuit. This DRAM circuit is used extensively in the electronics industry, and particularly in the computer industry for electrical data storage. The DRAM circuits consist of an array of individual memory cells, each cell consisting of an access transistor, usually a field effect transistor (FET), and a single storage capacitor. Information is stored on the cell as charge on the capacitor, which represents a unit of data (bit), and is accessed by read/write circuits on the periphery of the chip.
One conventional method to achieve a high density of memory cells on a DRAM chip is to form a capacitor node contact to one of the source/drain areas of the FET in each of the memory cells, and then to form a bottom electrode aligned over the node contact. In the next generation of semiconductor technology, the minimum feature sizes will be 0.25 micrometers or less. At these feature sizes, misalignment of the bottom electrode to the node contact can result in processing and reliability problems. One of these problems is best illustrated in the prior art depicted in FIGS. 1A through 3B. FIG. 1A shows a typical memory cell area on a substrate 10 having a silicon oxide (SiO.sub.2) first insulating layer 12 and a silicon nitride (Si.sub.3 N.sub.4) etch-stop layer 20. A patterned photoresist mask (not shown) and plasma etching are used to etch first openings 1 in layers 12 and 20 for node contacts. A doped first polysilicon layer is deposited and etched back to form the capacitor node contact 18 in opening 1. Because of variations in etch rate uniformities across the substrate, and because of nonuniformity in the polysilicon deposition, it is necessary to overetch for forming the polysilicon plugs for the node contacts to ensure that all the polysilicon is removed from the surface of the etch-stop layer 20. This results in recessed polysilicon plugs that expose the sidewalls of the first insulating layer 12. A disposable second insulating layer 22 is deposited, and a second photoresist mask 24 and plasma etching are used to etch second openings 2 in layer 22 for forming the capacitor bottom electrode, as shown in FIG. 1A. However, because of the difficulty of aligning the images for high-density circuits, the photoresist 24 for making the second opening 2' can be misaligned to the node contact 18, as shown in FIG. 1B.
Referring to FIGS. 2A and 2B, a conformal second polysilicon layer is deposited and polished back to form the capacitor bottom electrode 26. As shown in FIG. 2B for the misaligned opening 2', the disposable second insulating layer 22 is adjacent to and in contact with the first insulating layer 12 at point A.
Now, as shown in FIG. 3A, the disposable SiO.sub.2 second insulating layer 22 is removed using a wet etch, such as a hydrofluoric acid solution. The Si.sub.3 N.sub.4 etch-stop layer 20 prevents the etchant from attacking the first insulating layer 12 over the devices on the substrate. However, as shown in FIG. 3B for the misaligned opening 2' for the bottom electrode, when the second insulating layer 22 is etched, the first insulating layer 12 is also etched or eroded away at the point A, which can cause electrical shorts and other reliability problems. Therefore, it is desirable to modify the conventional method to prevent this oxide erosion problem.
There are numerous methods of making DRAM circuits with stacked capacitors that are reported in the literature. Several methods for making DRAM capacitors are cited below, but do not address this misalignment problem. Fazan, in U.S. Pat. No. 5,478,772 forms a stacked capacitor compatible with high-dielectric constant materials. In a second patent to Fazan et al., U.S. Pat. No. 5,281,549, a method for making an I-shaped stacked capacitor for maximizing surface area is described. Matthews et al., in U.S. Pat. No. 5,354,705, describe a method for making a stacked capacitor with rough inner and outer surfaces for increased capacitance. Jones et al., in U.S. Pat. No. 5,405,796, teach a method for making improved capacitors using advanced materials, such as ferroelectric materials or a high-permittivity dielectric.
Therefore, there is still a need to improve upon the conventional method for fabricating reliable DRAM capacitors on memory cells.